VHDL - 有限状態マシンXULA

Question

私はXULA2を持っており、いくつかのチュートリアルの後にLEDフラッシュをオン/オフすることに成功しました。今私は前進し、ステートマシンを実装しようとしています（基本的には同じことを行う - 今のところ）。いくつかの警告を受けて、最終的にビルドが出力ファイルを生成しません。

WARNING:Xst:1710 - FF/Latch <wait_time_msec_7> (without init value) has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1710 - FF/Latch <wait_time_msec_8> (without init value) has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process... 
WARNING:Xst:1710 - FF/Latch <wait_time_msec_15> (without init value) has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1293 - FF/Latch <fsm_display_1> has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1293 - FF/Latch <fsm_display_0> has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1293 - FF/Latch <cntr_time_delay_19> has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process.... 
WARNING:Xst:1293 - FF/Latch <cntr_time_delay_0> has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1710 - FF/Latch <wait_time_msec_9> (without init value) has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process.... 
WARNING:Xst:1710 - FF/Latch <wait_time_msec_0> (without init value) has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <blinker_o> (without init value) has a constant value of 0 in block <BigDisplayMain>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <return_state_0> is unconnected in block <BigDisplayMain>. 

：

エラーフォーム（いくつかの同様の警告が明確にするために除去される）です。

私は未使用の値がそれらが私を気にしないように、いくつかは、フリップフロップをトリミング発生する可能性がある理由ラフ理解している...多くの（私はこれについて疑問を持っていますが、私の主な問題が解決され、後にした後）

私のコードを簡単に説明すると、それは4状態の状態マシン - INIT, START0, START1 and DELAYです。私がしたいのは、デバイスがINITで始まり、START0からDELAYからSTART1からDELAYまでのループに進み、START0などに戻り、途中でLEDに信号を切り替えます（blinker_o経由）。確かに、これはLEDを点滅させるのに必要以上に複雑な方法ですが、DELAY状態を中心に、より洗練された作業を行う方法を学ぶにつれて学問的な練習です。

とにかく、コンパイラはblinker_oが '0'（WARNING:Xst:1895）にハードワイヤードされていると結論付けました。もちろん、これは私が好きなものではありません！

私はあなたの時間と支援が評価されて

（信号を「リセット」に残すこと以外の）問題を説明するために同じくらい私はできる限り自分のコードをストリップダウンしました！この設計をシミュレートしているようにあなたが表示されません

---------------------------------------------------------------------------- 
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
use IEEE.NUMERIC_STD.ALL; 

library UNISIM; 
use UNISIM.VComponents.all; 

entity BigDisplayMain is 
    port (  clk_i : in std_logic; 
       blinker_o : out std_logic 
     ); 
end BigDisplayMain; 

architecture Behavioral of BigDisplayMain is 

signal  clk_1MHZ : std_logic; 
signal   reset : std_logic := '0'; 
signal wait_time_msec : natural range 0 to 1_000_000; 
signal cntr_time_delay : natural range 0 to 1_000_000; 

type fsmA is (
FSM_INIT, FSM_STATE_DISPLAY_START0, FSM_STATE_DISPLAY_START1, FSM_STATE_DELAY 
); 
signal fsm_display : fsmA; 
signal return_state : fsmA; 

begin 
    -- DCM_CLKGEN: Frequency Aligned Digital Clock Manager 
    --    Spartan-6 
    -- Xilinx HDL Language Template, version 14.7 

    reset <= '0'; 

    DCM_CLKGEN_inst : DCM_SP 
    generic map (
     CLKFX_DIVIDE => 24,  -- Divide value - D - (1-256) 
     CLKFX_MULTIPLY => 2  -- Multiply value - M - (2-256) 
    ) 
    port map (
     CLKFX => clk_1MHZ,   -- 1-bit output: Generated clock output 
     CLKIN => clk_i,   -- 1-bit input: Input clock 
     RST => '0'    -- 1-bit input: Reset input pin 
    ); 

    -- End of DCM_CLKGEN_inst instantiation 

process(clk_1MHz, reset) is 
begin 
    if reset = '1' then 
     cntr_time_delay <= 0; 
     fsm_display <= FSM_INIT; 
     wait_time_msec <= 0; 
     blinker_o <= '0'; 

    elsif rising_edge(clk_1MHZ) then 
     case fsm_display is 
      when FSM_INIT => 
       cntr_time_delay <= 0; 
       wait_time_msec <= 0; 
       return_state <= FSM_STATE_DISPLAY_START0; 

      when FSM_STATE_DISPLAY_INIT_START0 => 
       blinker_o <= '0'; 
       wait_time_msec <= 1_000_000; 
       return_state <= FSM_STATE_DISPLAY_START1; 
       fsm_display <= FSM_STATE_DELAY; 

      when FSM_STATE_DISPLAY_INIT_START1 => 
       blinker_o <= '1'; 
       wait_time_msec <= 999_999; 
       return_state <= FSM_STATE_DISPLAY_START0; 
       fsm_display <= FSM_STATE_DELAY; 

      when FSM_STATE_DELAY => 
       if cntr_time_delay >= wait_time_msec then 
        fsm_display <= return_state; 
        cntr_time_delay <= 0; 
       else 
        cntr_time_delay <= cntr_time_delay + 1; 
        fsm_display <= FSM_STATE_DELAY; 
       end if; 

      when others => 
       null; 
     end case; 

    end if;  
end process; 
end Behavioral; 

Answer 1

：

は、ここでは、コードです。

私はそれと選択肢で列挙名に分析：私は選択肢を修正

type fsmA is (
FSM_INIT, FSM_STATE_DISPLAY_START0, FSM_STATE_DISPLAY_START1, FSM_STATE_DELAY 
); 

：タイプFSMAの宣言ではありません

  when FSM_STATE_DISPLAY_INIT_START0 => 

と

  when FSM_STATE_DISPLAY_INIT_START1 => 

を宣言されたfsma状態に一致させ、インスタンス化されたコンポーネントをコメントアウトし、clk_iをclk_1MHZに割り当て、小さなテストベンチを書いた：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
-- use IEEE.STD_LOGIC_UNSIGNED.ALL; 
-- use IEEE.NUMERIC_STD.ALL; 
-- 
-- library UNISIM; 
-- use UNISIM.VComponents.all; 

entity BigDisplayMain is 
    port ( 
     clk_i:  in std_logic; 
     -- reset:  in std_logic; 
     blinker_o: out std_logic 
     ); 
end BigDisplayMain; 

architecture Behavioral of BigDisplayMain is 

signal  clk_1MHZ: std_logic; 
signal   reset: std_logic := '0'; -- COMMENT out if driven by testbench 
signal wait_time_msec: natural range 0 to 1_000_000; 
signal cntr_time_delay: natural range 0 to 1_000_000; 

type fsmA is (
    FSM_INIT, 
    FSM_STATE_DISPLAY_START0, 
    FSM_STATE_DISPLAY_START1, 
    FSM_STATE_DELAY 
); 
signal fsm_display: fsmA; 
signal return_state: fsmA; 

begin 
    -- DCM_CLKGEN: Frequency Aligned Digital Clock Manager 
    --    Spartan-6 
    -- Xilinx HDL Language Template, version 14.7 

    reset <= '0'; -- COMMENT out if driven by test bench 

    -- DCM_CLKGEN_inst: DCM_SP 
    -- generic map (
    -- CLKFX_DIVIDE => 24,  -- Divide value - D - (1-256) 
    -- CLKFX_MULTIPLY => 2  -- Multiply value - M - (2-256) 
    --) 
    -- port map (
    -- CLKFX => clk_1MHZ,   -- 1-bit output: Generated clock output 
    -- CLKIN => clk_i,   -- 1-bit input: Input clock 
    -- RST => '0'    -- 1-bit input: Reset input pin 
    --); 

    -- End of DCM_CLKGEN_inst instantiation 

    clk_1MHZ <= clk_i; -- ADDED debug 

    process(clk_1MHz, reset) is 
    begin 
     if reset = '1' then 
      cntr_time_delay <= 0; 
      fsm_display <= FSM_INIT; 
      wait_time_msec <= 0; 
      blinker_o <= '0'; 

     elsif rising_edge(clk_1MHZ) then 
      case fsm_display is 
       when FSM_INIT => 
        cntr_time_delay <= 0; 
        wait_time_msec <= 0; 
        return_state <= FSM_STATE_DISPLAY_START0; 
        fsm_display <= FSM_STATE_DELAY; -- ADDED branch 

       when FSM_STATE_DISPLAY_START0 => -- REMOVED _INIT 
        blinker_o <= '0'; 
        wait_time_msec <= 10; -- 1_000_000; -- FOR SIMULATION 
        return_state <= FSM_STATE_DISPLAY_START1; 
        fsm_display <= FSM_STATE_DELAY; 

       when FSM_STATE_DISPLAY_START1 => -- REMOVED _INIT 
        blinker_o <= '1'; 
        wait_time_msec <= 9; -- 999_999; -- FOR SIMULTION 
        return_state <= FSM_STATE_DISPLAY_START0; 
        fsm_display <= FSM_STATE_DELAY; 

       when FSM_STATE_DELAY => 
        if cntr_time_delay >= wait_time_msec then 
         fsm_display <= return_state; 
         cntr_time_delay <= 0; 
        else 
         cntr_time_delay <= cntr_time_delay + 1; 
         fsm_display <= FSM_STATE_DELAY; 
        end if; 
       when others => 
        null; 
      end case; 
     end if;  
    end process; 
end architecture Behavioral; 

library ieee; 
use ieee.std_logic_1164.all; 

entity bigdisplaymain_tb is 
end entity; 

architecture foo of bigdisplaymain_tb is 
    signal clk_i:  std_logic := '0'; 
    -- signal reset:  std_logic := '0'; 
    signal blinker_o: std_logic; 
begin 
CLOCK: 
    process 
    begin 
     wait for 500 ns; 
     clk_i <= not clk_i; 
     if now > 120 us then 
      wait; 
     end if; 
    end process; 

    DUT: 
     entity work.bigdisplaymain 
      port map (
       clk_i => clk_i, 
       -- reset => reset, 
       blinker_o => blinker_o 
      ); 

-- STIMULI: 
--  process 
--  begin 
--   wait for 1 us; 
--   reset <= '1'; 
--   wait for 1 us; 
--   reset <= '0'; 
--   wait; 
--  end process; 

end architecture; 

最も重要なのは、私は、状態FSM_INITからSTATE_DELAYへの分岐を追加しました：

   when FSM_INIT => 
        cntr_time_delay <= 0; 
        wait_time_msec <= 0; 
        return_state <= FSM_STATE_DISPLAY_START0; 
        fsm_display <= FSM_STATE_DELAY; -- ADDED branch 

このブランチがなければ、それは一種のそこに座っていました。9および10に短絡時間遅れで

これは与える：

をそれはすべてあなたの合成の警告とフリップが食べられてフロップ用の状態FSM_INITで不足している支店が担当して可能性があります。それらのどれも使用されておらず、blinker_oがリセット値になります（リセットが実際に使用されたと仮定して）。