ベクトルの入力と配列を強制する方法

Question

ベクトルの配列を入力または強制する方法を知っている人はいますか？私はそれがそうだと信じていますが、うまくいきません。

--------- Test Bench --------------- 

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
use work.mypackage2.all; 

ENTITY test_bench IS 
PORT (H : in enter_vector := ("1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101"); 
     L : in enter_vector := ("1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101","1100","0011","1111","1101"); 
     X : out integer); 
END entity; 
ARCHITECTURE comportamento OF test_bench IS 



COMPONENT MUX is 
    Port (SEL : in STD_LOGIC; 
      H : in enter_vector; 
      L : in enter_vector; 
      X : out enter_vector; 
       Sinal: out std_logic -- it is 1 if H and 0 if L 
      ); 
END COMPONENT; 


COMPONENT choose is 
    Port (SEL : in STD_LOGIC; 
      E : in enter_vector; 
      X : out integer); 
END COMPONENT; 

signal VC : enter_vector; 
signal sin,sel: std_logic; 



BEGIN 

m: MUX PORT MAP (sel,H,L,VC,sin); 
cc: choose PORT MAP (sin,VC,X); 




END comportamento; 

------- Type Created----- 

    library IEEE; 
    use IEEE.STD_LOGIC_1164.all; 

    package mypackage2 is 

       type enter_vector is array (15 to 0) of std_logic_vector(3 downto 0); -- array of bytes 

    end mypackage2; 


    package body mypackage2 is 

    end mypackage2; 

Answer 1

の代わりにこの：

type enter_vector is array (15 downto 0) of std_logic_vector(3 downto 0); 
--        ^
--        | 

これは、VHDLで "落とし穴" 厄介です：

type enter_vector is array (15 to 0) of std_logic_vector(3 downto 0); 
--       ^
--        | 

あなたがこれを必要としていました。 downtoの代わりにtoを使用するのはエラーではありませんが、長さが0の配列になります。これにより、通常はコード内の他の場所でエラーが発生します。